1. Field of the Invention
The present invention relates to a semiconductor memory device that has a single or a plurality of memory cell arrays each configured such that a plurality of nonvolatile memory cells are arranged in each of a row direction and column direction, and a plurality of word lines and a plurality of bit lines are arranged in each of the row direction and column direction to select a predetermined memory cell or predetermined memory cells from the plurality of memory cells. More specifically, the present invention relates to an erase method for a memory cell array using variable resistor elements as memory bearers.
2. Description of the Related Art
Recent semiconductor memory devices are in a fast-growing field. Especially, flash memories can be electrically reprogrammed, and data once programmed therein are not erased even after power-off. Because of these features, flash memories are used with easy-to-carry memory cards and cellular phones, wherein they exhibit functions as, for example, data storage and program storage for non-volatilely storing data of device-operation initialization.
As memory cells of a flash memory, ETOX (registered trademark of Intel Corp., USA) type memory cells are known. As shown in FIG. 9, an ETOX type cell is configured such that a source 3 and a drain 2 is formed in a semiconductor substrate 1, and the source 3 and the drain 2 have a polarity opposite to the semiconductor substrate 1. In source-drain region, a gate insulation film 4 is formed; and further, a floating gate 5, an interlayer insulation film 6, and a control gate 7 are formed thereon.
According to the principles of operation of the ETOX type cell 10, in a data-program mode, ordinarily a low voltage (0V, for example) is applied as a source voltage Vs to the source 3, a drain voltage Vd (6V, for example) is applied to the drain 2, and a high voltage Vp (12V, for example) is applied to a control gate 7. At this time, hot electrons and hot holes are generated in a drain-source region. The hot holes flow as substrate currents into the substrate. The hot electrons are injected into the floating gate, thereby a threshold voltage as viewed from the control gate 7 is increased.
In a read mode, a low voltage (0V, for example) is applied as a source voltage to the source 3; a drain voltage (1V, for example), which is slightly higher than the source voltage, is applied to the drain; and a voltage of 5V is applied to the control gate 7. At this time, thresholds of a programmed cell and unprogrammed cell are different from each other, so that depending on the cell, there occurs a difference in the current flowing into the drain-source region. The difference is sensed for state determination. As a result, a state where the current is larger than a predetermined current is determined to be “1” (erased cell), and a state where the current is smaller than the predetermined current is determined to be as “0” (programmed cell).
In the erase mode, a high voltage Vpp (12V, for example) is applied to the source 3, a low voltage (0V, for example) is applied to the control gate 7, and the drain is maintained in a floating state. Thereby, a Fowler-Nordheim current flows to a floating gate-source region via a tunnel oxide layer 4, thereby causing electrons to be removed from the floating gate 5.
According to the operational principles described above, verify is performed whether cells to be programmed and erased are each in the state higher than the predetermined threshold or lower than the predetermined threshold. In program verify, a cell of interest is compared with a cell (reference cell) set to a high threshold (Vthp) (5.3V, for example). As a result, if the threshold of the cell of interest is higher than the reference cell threshold, the cell is determined as a programmed cell. In erase verify, a cell of interest is compared with a cell (reference cell) set to a low threshold (Vthe) (3.1V, for example). As a result, if the threshold of the cell of interest is lower than the reference cell threshold, the cell is determined to be an erase cell.
FIG. 10 is a configuration view of a source-common memory cell array section used in a conventional example of the flash memory. Address signals are input to a word decoder 11, data and address signals are input to a column decoder 12, and an erase signal is input to an erase circuit 13. This chip has m word lines WL1, . . . , WLm (m=2,048, for example), wherein control gates of n memory cells MC (n=512, for example) are connected to each one of the word lines. As such, the chip has n bit lines BL1, . . . , BLn. That is, the memory capacity of the memory is m×n pieces (1 Mb, for example). The source of the memory cell array is common, and a common source line SL is connected to the erase circuit 13. In the erase mode, an erase signal is input to the erase circuit 13; and as shown in FIG. 10, Vpp is applied to the sources of memory cell transistors arranged in an array, whereby all the cells can be erased at the same time.
In a practical device, erase is performed in units of a block, of which size is as relatively as large as 64 Kb, for example. In addition, a block to be erased contains memory cells having thresholds in programmed states and erased states, so that erase needs to be performed using a complex algorithm such as that shown in FIG. 11.
An erase method shown in FIG. 11 will be described hereinbelow. Upon the start of erase, a regular program operation (technique using CHE (channel hot electron)) is first performed to set all memory cells of one block to a programmed state (step S1). Program verify is then performed in units of, for example, eight bits, to verify whether thresholds of the memory cells programmed in step S1 are higher than 5.5V (step S2). If the thresholds of the memory cells are not higher than 5.5V, the processing returns to step S1 and continues programming. On the other hand, if the memory cell thresholds become higher than 5.5V, the processing proceeds to step S3. At step S3, erase pulses are applied in batch to the block. The erase is performed in such a manner that electrons are removed from the source side to lower the memory cell threshold. Then, at step S4, erase verify is performed to verify whether the thresholds of all the memory cells of the block are lower than 3.5V. If the memory cell thresholds are not lower than 3.5V, the processing returns to step S3 and continues erase. On the other hand, if the memory cell thresholds become lower than 3.5V, the processing terminates the erase.
As can be seen from the erase method shown in FIG. 11, all the cells are first processed to a programmed state in the manner that post-erase threshold distributions are tightened as much as possible; that is, the distribution widths are narrowed, and concurrently, an over-erased cells (cells whose thresholds becomes 0V or lower) is avoided. In this case, eight memory cells can be performed at the same time through regular program operations. When the programming time for one cell is assumed to be 2 μs, the time required for the program operations is 131 msec, as shown in expression (1) given below.2 μs×64 Kb÷8=131 msec  (1)
Assuming that an erase total time is 600 msec, the time for the program operations accounts for about 20% of the total time. For the verify at step S2, when the verify operations are performed with a per-cell verify time of 100 nanoseconds (ns) in units of eight bits, the verify time is about 6.6 ms, as shown in equation (2) below. For the erase pulse application of step S3, about a time of 300 msec is required.100 ns×64 Kb÷8=6.6 msec  (2)
For the erase method shown in FIG. 11, as a method of reducing the total time of pulse application, it is contemplated to increase the source application time in the event of erase pulse application. However, when the source voltage is increased, inter-band tunneling current is also increased, so that holes are trapped into the tunnel oxide layer, thereby leading to deterioration of reliability. For this reason, the source voltage cannot be increased higher than a given level, and hence the erase speed also cannot be enhanced.
A cellular phone is a representative example of application devices using a flash memory of the type described. Under conditions that force a device to use a power source with a significant capacity limitation placed to meet very strong miniaturization requirements as those for a cellular phone, a flash memory is suitable as it has the characteristic of nonvolatility that does not require a backup battery for information retention purposes even in a long standby time. In addition, because of increase in the storage capacity of the flash memory itself, the flash memory is capable of storing a large number of applications and a large amount of data and executing them by switching there among, thereby contributing to implementation of multi-functions of the cellular phone.
In the field of nonvolatile semiconductor memory devices of the type described above, there is a trend that application program and data themselves are increased in number and/or amount. In the future, it would be expected that a system capable of reprogramming software stored into a flash memory be put into practical use and the system be enabled to implement bug correction and/or functional upgrading. Under these circumstances, as in the case of the flash memory, with the semiconductor storage device that requires batch erase to be preliminarily performed to reprogram a file of program data and/or like, problems arise in that it takes a very long time for reprogramming. In addition, undue or superfluous storage capacity needs to be preserved for temporary buffering files. These things make procedures to be complex.